Multiphase clock

Multiphase clock

Dec

29

2009

I have found an interesting bug in my design that opened my eyes to one important aspect. The problem is related to the memory chips’ /WE (write enable) signal which should be asserted when I want to store data in memory. With nearly every TTL device in my design being synchronous, altering their states on ...
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Design · Design - control · Design - memory

Gate-level simulator

Gate-level simulator

Dec

22

2009

The simulator is ready and running first simulations of my CPU, proving for the first time that the envisioned mesh of wires and chips may actually work. Writing the simulator was not easy, but I think it was a great exercise. Not using Verilog for this purpose was not a bad idea at all. The ...
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Simulation