There is one aspect of logic design I’ve been totally neglecting, at least until now. It is related to unconnected (floating) inputs of certain families of 74-series chips. I realized this having read a couple of articles on the web, particularly this article comparing TTL and CMOS families, this class on allaboutcircuits.com, and this paper from Texas Instruments. I am not an electrical ...
Finally! It’s been 532 days (or 1 year, 5 months and 24 days) since my very first post here, and today I have a real, working machine, able to run programs and perform useful computations. Last night my CPU successfully executed the fibonacci program from this post from May (all homebrew CPU guys run fibonacci, right?). The code snippet ...
I reviewed the microcode while implementing the MDR workaround I discussed yesterday. I realized that the problem affects currently only 5 instructions, namely: ADD AH, (SP) SUB AH, (SP) CMP AH, (SP) SHL AH SHR AL I took advantage of MDR clearing whenever I manipulated the low or high byte of A register, using the ...
I have come across the first real design flaw in my CPU. By design flaw I mean a real design flaw, with something functioning not exactly as designed, not an accidentally swapped wire or a simple bug in schematics. The good news is that it going to be fairly easy to fix. The bad news ...
I think I am ready to declare readiness for a final countdown. For the last few weeks I have been hunting for bugs in my wiring and running all sorts of unit tests. I have completed the ALU board wiring, and I think the machine is very close to successfully running some kind of useful ...
It’s been nearly a month since I last posted. Unfortunately, there hasn’t been much progress recently. I have only a few hours every week which I can fully spend on project activities. Big part of the reason is that I will be moving from Poland to Germany for a while, and there is a lot ...
