Just a quick summary of what I have been doing over the last few sessions in the project.
New instructions
Before I continue with hardware I decided to add a few instructions I should have added a long time ago but somehow never got to it. The instructions are shorter versions of some load/store instructions I already have (like register indirect with immediate index, when index is implicitly zero). Also, I added register indirect with register index addressing mode ops, which will be absolutely necessary to access larger data structures like arrays. My hardware designs allows it, so this task required no change to the model – I just wrote appropriate microcode. To cut it short, below is a complete set of new instructions:
| Opcode | Mnemonic | Description | Flags set | Cycles |
| E6 | INC X | increase value of X | C,Z,N,V | 1 |
| E7 | DEC X | decrease value of X | C,Z,N,V | 1 |
| E8 | INC Y | increase value of Y | C,Z,N,V | 1 |
| E9 | DEC Y | decrease value of Y | C,Z,N,V | 1 |
| EA | LD A, (DP) | load A with memory at address in DP | 4 | |
| EB | LD A, (DP:X) | load A with memory at address in DP plus 16-bit signed offset in X | 4 | |
| EC | LD A, (DP:Y) | load A with memory at address in DP plus 16-bit signed offset in Y | 4 | |
| ED | ST (DP), A | store A in memory at address in DP | 4 | |
| EE | ST (DP:X), A | store A in memory at address in DP plus 16-bit signed offset in X | 4 | |
| EF | ST (DP:Y), A | store A in memory at address in DP plus 16-bit signed offset in Y | 4 | |
| F0 | LD AL, (DP) | load low byte of A with memory at address in DP | 2 | |
| F1 | ST (DP), AL | store low byte of A at address in DP | 2 |
As you can see I have also added handy increment and decrement instructions, which will be typically used in conjunction with register indirect with register index loads and stores.
Final test run
I decided to re-assemble and re-run a complete test suite for the machine, after having updated it with tests of new instructions. I was not surprised to find out that nearly every test file failed. This was due to the fact that the test suite assumed my previous, flat memory model. With paging enabled, one must initialize memory pages upon start of any test to even try to perform any data memory reads and writes. After these modifications (and fixing one more microcode assembler bug never discovered before) I was able to reach the point where each test completes successfully. Updated version of the test suite may be found here.
Fibonacci
Everybody runs some sort of Fibonacci code to prove their designs and hardware are functional and able to perform actual computation. Well, I decided to do the same so here is my version of the Fibonacci:
_start:
; setup stack
ld a, 0x5000
mov sp, a
; compute fibonacci(10)
ld a, 1 ; fib(1)
ld x, 0 ; fib(0)
ld y, 9
fibo:
push a
add a, x
pop x
dec y
jnz fibo
halt
Resulting simulator dump indicates a correct result of decimal 55 in register A (0x0037):
====== after cycle: 138 ==== time elapsed: 278000 ns ----------SIVNZC FLAGS: ********** * ** 01234567 IRQ: ZZZZZZZZ rst_: 1 stepcnt: 0x00 opcode: 0x001 fault_: 1 interrupt_: 1 pe: 0x00 microcode: 0x17cb5ff8 pbus: 0x00020012 abus: 0x10012 dbus: 0x00 lbus: 0x0000 rbus: 0x0012 aluresult: 0x0012 alubus: 0x0012 MAR: 0x0000 PC: 0x0012 PPC: 0x0011 SP: 0x0000 KSP: 0x5000 DP: 0xffff MDR: 0x0000 A: 0x0037 X: 0x0022 Y: 0x0000 Machine halted.
The Fibonacci code was added to the test suite. A complete updated software stack is available in downloads.