Still hundreds of wires to go

Still hundreds of wires to go

Jun

21

2010

Serious life has been keeping me busy recently, so wire wrapping progress is very slow. I only managed to lay out the control module and wrap few wires. At this speed looks like it will take me several months to complete so I need to find some time and progress more. Meanwhile, here are the ...
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Construction

Parts arrived, first wires wrapped

Parts arrived, first wires wrapped

Jun

11

2010

I received the CPU parts I ordered a few days ago. I think I have everything I need now, no more excuses. Surprisingly, all necessary TTL components were in stock at my electronic parts supplier. That’s more than 120 LS-type TTL integrated circuits. The parts come from different manufacturers, and some are of course second-hand, recycled ...
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Construction

Schematics

Schematics

Jun

6

2010

I have successfully come to an end of schematics drawing. It was a challenging task, considering I had zero experience in this matter and the final design is quite complex in terms of number of components and nets. In a hope I didn’t make many mistakes I am publishing the results today and declaring the ...
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Design

EAGLE Layout Editor

May

13

2010

I am using EAGLE to draw schematic diagrams of the CPU. The reason I chose EAGLE was simple – everyone uses it, it is free (or inexpensive under non-profit license), and has a rich component library. Also, most PCB manufacturers accept EAGLE files, and if not, there are many scripts to output gerber files. So, if ...
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General

New instructions, final test run and Fibonacci

May

2

2010

Just a quick summary of what I have been doing over the last few sessions in the project. New instructions Before I continue with hardware I decided to add a few instructions I should have added a long time ago but somehow never got to it. The instructions are shorter versions of some load/store instructions I ...
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Design - ISA · Simulation

Memory module 2

Memory module

Apr

24

2010

I have completed the design of the memory module – the last required module to announce the entire design finished. I chose a very simple design, with rudimentary paging mechanism, in a hope it will not turn out to be a significant limitation in the near future. The machine features a 22-bit physical address bus, ...
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Design · Design - memory