I found a nasty design bug yesterday. Some time ago, when I was approaching the end of preliminary hardware verification, having successfully completed tests for most of the instructions, I suddenly bumped into the wall. Problems occurred when I was trying to exercise my faults and interrupts mechanism. It didn’t work at all, causing the system to oscillate and behave in a manner far from what I had designed. After some time I was able to track down the problem close enough to know that incorrect behavior occurred while trying to latch a logic low state to the /FI status flag (to enable faults and interrupts). I spent long hours trying to locate the bug – replacing parts, inspecting connections with a magnifying glass, unwiring and rewiring, calculating fanout – no luck. The system was switching the microcode storage to faults/interrupts space not exactly at the right moment, and latching /FI and /FS flags produced incorrect results. This is just to name a few problems the bug was causing.
The solution came to me yesterday, out of nowhere and totally by accident. I was reviewing the 74LS74 datasheet to check data setup and hold times, as well as its input currents when I realized I made the same kind of mistake I had previously made with 74LS173 chip (see this post from December). I wrongly assumed that the 74LS74 flip-flop’s /PRE and /CLR inputs are synchronous and are used to latch a high or low state respectively on a positive clock edge. This assumption exists in my simulator code, schematics and wire-wrapped hardware. Unfortunately, 74LS74 does not behave this way. Both inputs are asynchronous, and high or low state is not latched even if they are asserted during positive clock transition. The only relevant input for latching is the flip-flop’s D input. Period. Had I ever taken any university course on digital electronics, I would have known. Lack of experience got me gain. The lesson learned for me is – always read the datasheet, and do it carefully.
Just for the record, here is a truth table for a real 74LS74 flip-flop:
| Inputs | Outputs | ||||
| /PRE | /CLR | CLK | D | Q | /Q |
| L | H | X | X | H | L |
| H | L | X | X | L | H |
| L | L | X | X | H* | H* |
| H | H | ↑ | H | H | L |
| H | H | ↑ | L | L | H |
| H | H | L | X | Q0 | /Q0 |
And my flavor of it which I used in the design:
| Inputs | Outputs | ||||
| /PRE | /CLR | CLK | D | Q | /Q |
| L | H | ↑ | X | H | L |
| H | L | ↑ | X | L | H |
| L | L | ↑ | X | Q0 | /Q0 |
| H | H | ↑ | H | H | L |
| H | H | ↑ | L | L | H |
| H | H | L | X | Q0 | /Q0 |
This issue slowed me down quite a bit. I was assuming to complete hardware testing by end of January. It’s not going to happen. Currently I am fixing the schematics to account for a “real” 74LS74, then I will update the simulator code and simulate the whole thing again. Consequently, I will have to rewire significant parts of microcode sequencer and the MSW register. These are the two places in my design where the non-existent flip-flop which I accidentally invented was used. I wired both of them some time ago, and there is lots of other wires on top so this task may be no fun at all.
Edit:
I was not quite right about the behavior of /PRE and /CLR inputs. A quick breadboard test revealed that both inputs do latch high or low state, respectively. Unfortunately, I can also confirm that they do it asynchronously, which is not what I need.
Well, In my own experience, PRESET and RESET inputs are, in fact asynchronous, and active low, but… they do latch… that for sure! –As a mater of fact, I have used this chip as simple SR flip-flop by connecting CLK and D both to ground. The only tricky thing is that (as the datasheet makes clear about it), the FF is not going to behave as expected when both PRESET and RESET are active as the same time.
Moreover, the HCMOS implementation of th chip (74ACT74, the one I used for Heritage/1 and now for LC-81) behaves diferently: putting those two inputs to low won’t give you any trouble, only that PRESET has preference, that is, in such a case, Q goes high an /Q goes low.
I would suggest to setup a little test on bread board to make sure what the exact behavior of your 74LS74 chip is.
I’m glad you’re still on the battle field.
Armando, you are absolutely right. As suggested, I set up a little breadboard test and verified the behavior of both inputs (PRESET, CLEAR). In fact, they do latch regardless of the clock, and the only unstable condition is when they are both pulled low (I tested with 74LS74 TTL). Unfortunately, I need them to only latch on positive clock edge, so rework is unavoidable.